The present invention relates to a dynamic random access memory (DRAM) having a refresh control function. Particularly, this invention relates to a DRAM having a refresh control function to limit excess refresh operations.
DRAM cells store data as charges that are reduced due to junction leakage, etc. Therefore, DRAMs require a refresh operation for reading and rewriting cell data from and to each cell.
The following are major two types of DRAM refresh:    (A) external address entry to initiate refresh operation; and    (B) internal address generation for refreshing with a built-in-chip address-counter, with no external address entry.
The type (A) includes RAS-only refresh, CAS before-RAS refresh, etc.
RAS-only refresh is to input row addresses in synchronism with row-address strobes (abbreviated as *RAS hereinafter) to select and drive each word line.
CAS before-RAS refresh is to make column-address strobes (abbreviated as *CAS hereinafter) at level “LOW” prior to *RAS in refreshing while *RAS and *CAS are always appearing at different timings.
The symbol “*” added to each signal indicates that the signal has been inverted. For example, *RAS means that a signal RAS has been inverted.
The type (B) includes auto refresh, self refresh, etc.
Auto refresh is to generate internal addresses for refreshing, in synchronism with a control signal given via a refresh-control terminal during a period of level “HIGH” (inactive period) for *RAS.
Self refresh is to generate internal addresses for refreshing per specific period of time with an internal timer.
A known DRAM having a refreshing function is DYNAMIC TYPE SEMICONDUCTOR MEMORY disclosed in Japanese Unexamined Patent Publication No. 5-109268.
The known DRAM is a type-(B) DRAM, having a memory-cell array divided into several memory subarrays with different refreshing periods per sub array, to limit excess refresh operations for reduction of power consumption.
The type-(A) refresh requires external addresses but flexible in selection of refreshing regions in cell array.
In contrast, the type-(B) refresh inhibits selection of refreshing regions, thus requiring refreshing to all regions in Dram chip, including no-data-stored regions. The type-(B) refresh thus causes excess refresh operations to increase power consumption.
The known DRAM is provided with different refreshing periods to avoid such excess refresh operations. Nevertheless, the known DRAM is not equipped with a refresh-control function in accordance with frequency in use of DRAM chip regions. In particular, it is not equipped with a function of halting unnecessary refreshing to no-data-stored regions.